Generally speaking, computer systems typically include one or more central processor units (CPUs). Each CPU includes many signal paths that convey data between functional units or logic circuits that operate on that data. Such data is typically conveyed using a clocked circuit that operates in conjunction with a specified data transfer timing structure. That timing structure dictates a time period when the data to be transferred is valid. Accordingly, the data must be captured while it is valid to ensure functionality of the associated CPU. Such time periods when data is valid are typically identified by particular assertions of system clock signals.
When data is to be transferred from one logic circuit to another, the clock signal that clocks the sending or driver unit is typically distinct from the clock signal that clocks the receiving unit. Although both clock signals assert at essentially the same frequency, significant differences may occur between assertion times based primarily on the fact that they are generated by different clocking circuits. Even when those clocking circuits are substantially similar, differences can arise based upon resistance, capacitance or inductance differences, or based upon resistance, capacitance and inductance differences, or based upon temperature, voltage, or process variances. The difference between the assertion times of the two clock signals is referred to as xe2x80x9cclock skewxe2x80x9d.
In the case of such data transfers, it is desired that data is transferred as quickly as possible such that peak performance may be achieved. Accordingly, data is typically transferred in a single clock period, or clock phase, wherein the driver unit generates the data in response to a first clock assertion (or edge) and the receiving unit latches the data on the next clock assertion (or edge). Such a data transfer strategy can remain operable in the presence of clock skew if that clock skew causes the clock signal coupled to the receiver unit (the receiving clock) to assert before the clock signal coupled to the driver circuit (the driving clock). In that case, the data output by the driver circuit has not yet begun to change and therefore the receiver unit latches valid data.
However, the above-mentioned data transfer methodology can be frustrated when clock skew causes the receiving clock signal to assert after the driving clock signal. Such a data transfer will typically fail because it is possible for the receiver circuit to latch the data after it has become indeterminate. Such an effect is referred to as a xe2x80x9crace-throughxe2x80x9d condition since it causes a race between the data becoming indeterminate and the receiver circuit attempting to latch valid data. Accordingly, the data that is latched depends upon the speed at which the data is changing and therefore cannot be relied upon for robust data transfer operations.
When a clocked circuit contains a race-through condition, data transfers will typically not be able to complete regardless of the frequency at which the circuit is operated. Accordingly, when a race-through condition occurs within a clocked circuit of a semiconductor device, even basic functionality of that device cannot be exercised. Typically, the clocking strategy of a semiconductor device is heavily simulated before device fabrication is initiated in an attempt to avoid the above-mentioned problems. However, regardless of the amount of simulation, process and environmental variances can still cause the clock skewing to cause a race-through problem.
Prior art approaches for eliminating the effects caused by clock skew, referred to as a de-skewing operation, have proved problematic. For example, one method for de-skewing the clock signals involves preventing newly generated data from being presented to the receiver device until the previously generated data has been latched. In other words, new data that is generated by the driver device is delayed or gated until the receiving clock signal has asserted. Such an approach eliminates the effects caused by clock skew at the expense of significantly extended data transfer times. In other words, the data transfer is delayed by at least the time difference between the assertions of the two clock signals, i.e., by the duration of the clock skew.
The prior art de-skewing circuits do not provide a temporary solution but rather become a permanent part of the clocked circuit. The solution becomes permanent because it is difficult to predict whether a given circuit modification, designed to prevent such clock skew, will be effective in the presence of different environmental variations. Accordingly, because it cannot accurately be determined whether the clock skew has, in fact, been corrected, peak performance of the circuit is thereafter limited by the speed of the de-skewing circuit.
Generally a method is provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when excessive clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing the functionality from the circuit.
With a preferred embodiment of the invention an apparatus is provided for ensuring functionality of a clocked circuit without limiting its peak performance. The apparatus includes a de-skewing device that receives a data signal to be transferred to a receiver device. That data signal is generated by a driver device at a time that is indicated by an assertion of a driving clock signal. The de-skewing device simply buffers the data signal with minimal delay when a mode select signal is de-asserted, indicating the absence of a clock skew problem. The de-skewing device alternatively gates the data signal until a receiving clock signal is asserted to ensure that the receiver device latches valid data.
The driving clock signal and the receiving clock signal may be generated by different clock circuits. When different clock circuits are employed, differences can arise between the assertions of the clock signals. Those differences are referred to as clock skew.
With a further aspect of a preferred embodiment, the driver device and the receiver device can be implemented using edge triggered sense amplifiers.
The clocked circuit can further include a logical-or circuit for performing a logical-or function between the receiving clock signal and the de-skew mode signal such that the de-skew device will perform the buffer operation when the mode select signal is de-asserted. When the mode select signal is de-asserted, the clocked circuit can operate at peak performance. Alternatively, the de-skewing device will perform the de-skewing operation when the mode select signal is asserted.
Because the mode select signal can be selectively asserted or de-asserted, the de-skewing device and the logical-or circuit may remain coupled to the clocked circuit even in a production version of that clocked circuit without limiting its peak performance.
With a still further aspect of an embodiment of the present invention, a logic function is performed on the data signal output from the de-skewing device before it is conveyed to the receiver device.
Accordingly, a semiconductor device that includes such a selectable de-skewing device is ensured to be functional regardless of the presence of clock skew.